Silicon is commonly used as a substrate material for the fabrication of integrated circuits. Devices are continually being scaled down in size, including in the vertical direction by reducing gate oxide thickness and in the horizontal direction by reducing channel length. Device power supply voltage (Vdd) is also being reduced to reduce power consumption.
Silicon material properties, as well as integrated circuit processing capabilities, restrict the shrinking of silicon-based devices. These limiting properties include the intrinsic carrier mobility of silicon [μn=−1450 centimeter2 * volts−1 * second−1 (cm2V−1s−1) and μp=450 cm2V−1s−1, where μn=mobility of n-type carriers and μp=mobility of p-type carriers] which sets the achievable cutoff frequency to less than 160 Gigahertz (GHz) for a gate length of 30 nanometers (nm).
Power dissipation increases as threshold voltage (Vt) decreases. Two major components of power dissipation are dynamic capacitive switching and static off-state leakage current. Dynamic power dissipation can be expressed as Pd=CV2f, where C=capacitance, V=operating voltage, and f=repetition frequency. Lowering V decreases dynamic power dissipation, but the effect is offset by higher operating frequency and increased C due to the vertical scaling down of gate dielectric thickness.
Leakage current primarily comprises subthreshold conduction in off-state (Isub), reverse bias pn junction conduction (ID), and tunneling through gate dielectrics(Ig) Subthreshold conduction occurs when a MOSFET device is operated with a Vg below Vt. Subthreshold conduction is proportional to the weak inversion carrier density ˜e−φs/kT, where φs=electric potential at semiconductor surface, k=Boltzmann's constant, and T=temperature, with φs being proportional to the difference between Vg and Vt. During the process of lowering the operating voltage, Vt should also be lowered to maintain the V/Vt ratio for sufficient current gain. An adverse consequence is that subthreshold leakage current increases exponentially with decreasing Vt.
Reverse bias leakage current occurs at reverse biased drain/well and source/well junction regions. It is caused by thermal generation in depleted regions and by diffusion of minority carriers across reverse biased junctions. This leakage is especially problematic at the source and channel well regions when the channel length is so short that the electric field of the drain to source voltage effectively lowers the barrier across the source/channel depletion region and causes large offstate leakage current. This is commonly called drain induced barrier lowering effect for short channel devices.
Tunneling leakage is due to quantum mechanical tunneling of electron wavefunction across a gate dielectric. Tunneling leakage is expected to increase as conventional silicon dioxide (SiO2) gate dielectrics shrink in a vertical dimension. This tunneling leakage current will become a dominant source of off-state leakage when conventional silicon dioxide layers are scaled down below an effective oxide thickness (Tox) of 1.6 nm.
These static power dissipation effects become a significant portion of the total power dissipation in increasingly smaller and highly packed logic products.